It has been known for many years that extremely high voltages (e.g. 10,000 volts or greater) can develop in the vicinity of an integrated circuit (IC) due to the build-up of static charge. Electrostatic discharge (ESD) refers to the phenomenon whereby an electrical discharge of high current and short duration is produced at the package nodes of an integrated circuit, as a consequence of static charge build-up on that IC package or on a nearby body such as a human being or an IC handling machine. Electrostatic discharge is a serious problem for semiconductor devices since it has the potential to disable or destroy the entire integrated circuit. Because ESD events occur most often across the silicon circuits attached to the package nodes, circuit designers have concentrated their efforts on developing adequate protection mechanisms for these sensitive circuits. Ideally, an ESD protection device should be able to protect an IC against any conceivable static discharge by passing large currents in a short time in a nondestructive manner.
One difficulty in designing ESD circuits is the demanding performance requirements which must be met. For example, one of the primary industry standards for measuring ESD robustness--MIL-STD-883C method 3015.7 Notice 8 (1989) and its follow-on standard no. 5.1 (1993) from the EOS/ESD Association--requires ESD "zapping" for what can be a large number of pin and power supply combinations. In the past, ESD protection circuits have had difficulty in meeting these stringent military standard performance requirements while maintaining adequate noise immunity.
Integrated circuits have come under pressure in these human body model (HBM) ESD tests because of repeated stressing of the power supply rails, leading to wearout of various breakdown points on, say, the Vcc lines. A reliable power supply clamp device is needed in order to take pressure off the rest of the Vcc bus during ESD stressing.
As will be seen, the present invention provides an ESD protection circuit which exceeds industry performance goals while allowing adequate noise immunity margins and product compatibility through the use of multiple power supplies.
Co-pending application Ser. No. 08/138,472 filed Oct. 15, 1993 relates to devices for protecting an integrated circuit (IC) against electrostatic discharge (ESD). The basic design of one device described in the co-pending application is capable of being implemented for a variety of different circuit protection requirements. For instance, in one embodiment the disclosed device can be used for protecting an input buffer only against an ESD event. In another embodiment, an output buffer of an integrated circuit can be protected and still in yet another embodiment, the ESD protection circuit can be utilized to protect a terminal of an integrated circuit which is capable of both receiving inputs and providing outputs as an external signal.
In each instance, the device disclosed in the aforesaid co-pending application includes as a key feature, a self-triggered silicon controlled rectifier (SCR) which is preferably coupled across the internal supply potentials of the integrated circuit. When the SCR has its anode coupled to a first supply potential and its cathode coupled to a second internal supply potential, the SCR exhibits a snap-back in its current versus voltage characteristic which is triggered at a predetermined voltage during an ESD event. As large voltages build up across the chip capacitance, the predetermined voltage of the SCR is triggered at a potential which is sufficiently low to protect the internal junctions of the IC from destructive reverse breakdown. At the point it triggers, the SCR provides a low resistance path between the first and second supply potentials.
In one embodiment, the SCR comprises a pnpn semiconductor structure which includes a n-well disposed in a p-substrate. A first n+ region and a p-type region are both disposed in the n-well. The n+ and p-type regions are spaced apart and electrically connected to form the anode of the SCR. Also included is a second n+ region. However, there are triggering difficulties which arise from the use of a SCR as a power supply clamp due to several reasons. First, there is a minimum SCR trigger voltage which is near the n+ junction breakdown voltage on the rest of the power bus, meaning that ESD current will usually be shared with other circuits on the power bus. Also, each SCR clamp has a minimum trigger current for the low voltage state. Thus, the power bus can become "hung up" near the (higher) trigger voltage due to the SCR's failure to reach the low voltage state, resulting in current sharing with the entire power bus.
In addition to the use of a SCR as a power supply clamp to provide ESD protection, over the past few years, it has become common to include diode strings, especially across power supplies, as part of routine ESD protection in products such as the 80486SL (Enhanced) microprocessor manufactured by Intel Corporation.
Diode strings have been used successfully to couple peripheral power supplies to their corresponding core power supplies during ESD events, while affording voltage isolation adequate to prevent unwanted coupling during ordinary operation. In their role as "charge couplers," they have enhanced charged device model (CDM) performance. More visibly, there is growing evidence that they help products with multiple, electrically separated power supplies to pass the multiple pin combination tests of the HBM ESD test, the most common industry standard test. Conversely, most products with multiple, electrically separated power supplies that have not, for one reason or another, used the diode strings have had difficulty passing the HBM pin combination tests. In these cases, failures have often been elusive, seeming to occur at random due to "wearout" of peripheral power buses. Better power supply clamping and better coupling of the charge to "safe" discharge paths seems to be needed. The following is an explanation of how the diode strings accomplish this and how certain enhancements can be used to expand and improve ESD protection.
A typical example of a diode string would be a Vsso (e.g., a noisy output supply) double-clamped to core, or substrate, Vss, as shown in FIG. 1a. The single diode is, of course, the n+ junction on the p-substrate, while the stack of four is a diode string cell. Also shown in FIG. 1b is a typical diode string between Vcco and a core Vcc. Notice that the Vsso-Vss arrangement is bidirectional (because of the parasitic diode), while the Vcco-Vcc coupling is unidirectional.
Diode string layout begins with a subcell, resembling the diode shown in a schematic top view in FIG. 2. The basic p-n junction is made with tightly spaced, minimum width p-diffusions and n+ taps of floating n-wells. A parallel combination of these cells forms a diode with the desired area, measured by taking account of the total length of metal-contacted p+ fingers opposite metal contacted n+ tap fingers. In this way, current density is measured in current per micron. Next, diodes are connected in series as shown in cross-section in FIG. 3. Each n-well is tapped and fed to the p+ junction of the next diode. Any number of p-n junctions can be strung together in this way (although there is a point of diminishing returns, as discussed below); for the purpose of this description, the 4-stage case, which is a common choice, is shown and described.
In FIG. 3, the floating wells also form an unavoidable rectifying junction with the substrate, with the result that the "diode string" is really a chain of Darlington-coupled PNP transistors, schematically shown in FIG. 4. This raises the question of the influence of the vertical current gain (.beta.) on diode string operation, which can be considerable. Indeed, it will be shown that the current gain can be used to formulate designs with improved efficiency and versatility. But first the p-n diode equations and temperature dependence need to be developed.
Basic diode behavior in terms of temperature dependence and current vs. voltage relationship will now be described to provide a further background necessary for an understanding of the present invention.
a. Temperature dependence
Starting with the p-n junction I-V relation: EQU I=Is (exp(qV/nkT)-1), where Is=Io exp (-Eg(T)/kT), [Eq. 1]
where n is the diode ideality factor (almost 1), Eg(T) the bandgap, T the absolute temperature, k is Boltzmann's constant and q the electronic charge. The -1 term can be ignored as long as V&gt;3kT/q, about 100 mV for a typical product temperature range. Any temperature dependence in Io is outweighed by the temperature dependence of the exponential factor that follows. Therefore, Eq. 1 can be written: EQU ln(l/Io)=(qV-nEg(T))/nkT, [Eq. 2]
and be assured that this quantity is nearly independent of temperature for a constant current I. In a typical product temperature range of interest (-55 C to 125 C), the silicon bandgap has been measured to be Eg(T)=Ego-bT, where Ego=1.206 eV and b=2.7325.times.10.sup.-4 eV/K as described by Y. P. Tsividis, "Accurate Analysis of Temperature Effects in Ic-Vbe Characteristics with Application to Bandgap Reference Sources", IEEE J. Solid State Circuits, SC-15, 1076-1084 (1980).
Ignoring a slight second order temperature correction that applies only below room temperature, Ego is therefore the extrapolated 0K bandgap and will henceforth be expressed in volts. Notice that if Eq. 2 is expanded out, the linear coefficient b contributes nothing to the temperature dependence of the right hand side, so another temperature-independent quantity is (qV-nEgo)/nkT.
This means that if the diode forward voltage Vf at absolute temperature T0 is known, the voltage at the same forward current can be easily calculated for another temperature T.sub.1 : EQU Vf(T.sub.1)=nEgo+(T.sub.1 /T0) (Vf(T0)-nEgo) [Eq. 3]
The temperature coefficient of Vf will thus be negative; typically T0 is room temperature and Vf is around 0.55-0.6 V for forward current of 1-10 .mu.A, giving a temperature coefficient for Vf around -2.2 mV/K.
b. Current vs. voltage
Diode ideality factor can be measured from a semilog plot of diode I vs. V, most conveniently done on an HP4145 Semiconductor Parameter Analyzer. An ideal diode (n=1) gives the well-known 60 mV/decade slope for low currents at room temperature (0.060 V.apprxeq.300 k ln(10)/q).
Once the single diode ideality factor is determined, the semilog I-V slope of a diode string is of interest. For a series of m diodes, it can be shown that the low current I-V slope is mnkT ln(10)/q volts per decade, or m.times.60 mV/decade for ideal diodes at room temperature. This result holds even with finite PNP current gain .beta., as long as .beta. is independent of current. As described below, the bipolar current gain just amplifies the current passed at a given voltage, in a manner depending only on .beta. itself.
Modeling the effect of transistor action, namely current gain and modeling in the leakage regime and in the ESD regime provides further useful insights into a proper understanding of the invention.
Current gain and modeling in the leakage regime
For an analysis of the effect of the PNP bipolar current gain, or .beta., on the performance of the diode string, a single stage of the Darlington-coupled series is shown in FIG. 5, with the usual relations shown for emitter, base, and collector currents:
Because the next diode stage has reduced current flowing into its emitter, the forward voltage in stage 2 will be reduced by an amount depending on .beta.: EQU ln(I.sub.1 /Is)=qV1/nkT; ln(I.sub.2 /Is)=qV2/nkT=ln (I.sub.1 /((.beta.+1)Is))=ln(I.sub.1 /Is)-ln(.beta.+1), so that [Eqs. 4] EQU V2=V1-(nkT/q) ln(.beta.+1), or V2=V1-ln(10) (nkT/q) log(.beta.+1).
Now let Vo=ln(10)(nkT/q), 60 mV for an ideal diode at room T. The analysis of Eqs. 4 is applied to multiple stages to give a loss of an additional Vo*log(.beta.+1) at each stage, resulting in a total voltage V.sub.t of a string of m identical diodes at current I.sub.1 of ##EQU1## where V.sub.1 is the base-emitter voltage for one diode (collector and base shorted) at emitter current I.sub.1. Obviously this model depends on a constant .beta. and no effect of series resistance, which are usually the case in the low leakage current range. The effect of temperature on diode string efficiency is clearly shown in FIG. 6 which plots out Eq. 5 for two temperatures.
Given some baseline diode data like ideality factor and forward voltage for a given current at a reference temperature (such as room T), the V.sub.1 at the temperature of interest can be calculated, and Eq. 5 applied. Equation 5, and the summation leading up to it, shows that a sizable .beta. results in a decreasing additional voltage for each succeeding diode stage, the reason being that the final stage has less and less emitter current, resulting in less and less voltage drop for that stage. The model breaks down when that voltage is so low that the -1 term in Eq. 1 becomes substantial again and the voltage of each additional stage goes to zero. Never does an additional diode actually subtract from Vt.
Current gain and modeling in the ESD regime
When an ESD pulse passes through the diode/transistors, the current density is many decades higher than in the leakage regime discussed above. There are not just microamps of leakage, but milliamps per micron of p+ finger length in the initial diode stage. In this regime, diode resistance effects become important, and current gain decreases.
The expected functional form of .beta. plotted against current density is shown in FIG. 7. When log .beta. is plotted versus log Je, the emitter current density, a linear declining slope results also. This also simplifies the modeling. The decline of .beta. with collector current density is expected in all bipolar transistors (See, W. M. Webster, "On the Variation of Junction-Transistor Current Amplification Factor with Emitter Current", Proc IRE 42, 914 (1954), quoted in S. M. Sze, Physics of Semiconductor Devices, 2nd edition (Wiley, 1981), pp. 142-143). The result is that there is high .beta. at low current, where it is undesired due to diode leakage, and low .beta. at high current, where .beta. allows ESD current to pass to the substrate. Nevertheless, with clever use of the design options, a competitive protection device can be devised within the available area.